Revista: IEEE TRANS. ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS. Vol.56. No.12. Pp.2634-2643. 2009

Autores: M. GARRIDO, K. PAHRI, J. GRAJAL

This paper presents a new pipelined hardware architecture for the computation of the real-valued fast Fourier transform
(RFFT). The proposed architecture takes advantage of the reduced number of operations of the RFFT with respect to the complex fast Fourier transform (CFFT), and requires less area while achieving higher throughput and lower latency.
The architecture is based on a novel algorithm for the computation of the RFFT, which, contrary to previous approaches, presents a regular geometry suitable for the implementation of hardware structures. Moreover, the algorithm can be used for both the decimation in time (DIT) and decimation in frequency (DIF) decompositions of the RFFT and requires the lowest number of operations reported for radix 2. Finally, as in previous works, when calculating the RFFT the output samples are obtained in a scrambled order. The problem of reordering these samples is solved in this paper and a  pipelined circuit that performs this reordering is proposed.