Congreso: 2005 IEEE International Radar Conference. Arlington, VA, USA. 9-12 de Mayo de 2005

Autores: M.A. Sánchez, M. Garrido, M. López-Vallejo, J. Grajal, C. López-Barrio.

This paper presents several implementations of digital channelised receivers on field-programmable gate array (FPGA) platforms for electronic warfare (EW) applications. All implementations are based on the fast Fourier transform (FFT) but they are intended for different applications. We have studied in detail and implemented different parallel architectures for the FFT algorithm in order to maximise speed processing and throughput, and to optimise area. On the other hand, monobit implementations of the FFT have been carried out in order to get real time in broadband digital receivers. Finally, in order to improve the detection of non-stationary signals, time-frequency analysis based on the short time Fourier transform (STFT) has also been implemented.