Congreso: 2006 European Conference on Wireless Technology. Manchester, UK Fecha: 10-12 Septiembre 2006.

Autores: D. Ramírez, J. Gismero

This paper describes a novel design approach for the DDS (direct digital synthesizer) required to correct the frequency shift in the received signal of a digital OFDM receiver. The traditional phase accumulator has been modified to perform modulus 2 N -1 accumulation. This modification provides fine frequency tuning capabilities using a very small sine/cosine look-up-table. Current systems use hundreds or thousands carriers requiring a DDS with very small frequency steps. This requires enormous amounts of memory for the sine/cosine LUT and an accumulator with many bits, limiting the maximum clock frequency. A reduction of required memory of more than 3 orders of magnitude can be achieved while an smaller phase accumulator allows for higher frequency operation. The design can deal also with systems where selectable carrier spacing is used such as DAB (digital audio broadcasting), with a minimal memory resource count increase. The design focuses on FPGA implementation although it may be applied also in an ASIC to achieve lower power and area reduction